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| fax id: 6128 For new designs see CY7C373i CY7C373 UltraLogicTM 64-Macrocell Flash CPLD Features * 64 macrocells in four logic blocks * 64 I/O pins * 6 dedicated inputs including 4 clock pins * Bus Hold capabilities on all I/Os and dedicated inputs * No hidden delays * High speed -- fMAX = 125 MHz -- tPD = 10 ns -- tS = 5.5 ns -- tCO = 6.5 ns * Electrically alterable Flash technology * Available in 84-pin PLCC and 100-pin TQFP packages * Pin compatible with the CY7C374 Functional Description The CY7C373 is a Flash erasable Complex Programmable Logic Device (CPLD) and is part of the FLASH370TM family of high-density, high-speed CPLDs. Like all members of the FLASH370 family, the CY7C373 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. The 64 macrocells in the CY7C373 are divided between four logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource--the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. Logic Block Diagram CLOCK INPUTS INPUTS 4 INPUT MACROCELLS 2 16 I/Os I/O0-I/O15 2 INPUT/CLOCK MACROCELLS 2 16 I/Os I/O48-I/O63 LOGIC BLOCK A 36 16 PIM 36 16 LOGIC BLOCK D 16 I/Os I/O16-I/O31 LOGIC BLOCK B 36 16 36 16 LOGIC BLOCK C 16 I/Os I/O32-I/O47 32 32 7C373-1 Selection Guide 7C373-125 Maximum Propagation Delay (ns) Minimum Set-up, tS (ns) Maximum Clock to Output, tCO (ns) Maximum Supply Commercial Current, ICC (mA) Industrial Shaded area contains preliminary information. 7C373-100 12 6 6.5 250 7C373-83 15 8 8 250 300 7C373-66 20 10 10 250 300 7C373L-66 20 10 10 125 10 5.5 6.5 280 Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 June 1992 - Revised April 20, 1998 |
Price & Availability of 7C373
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